This invention relates to a charge detecting device, and more particularly, to a charge detecting device in a charge coupled device in which an operating condition of a reset transistor is automatically controlled.
A structure and an operation of a typical charge detecting device in a prior art which may be applied to a solid state imaging device using a charge coupled device (CCD) will hereinafter fully be described in detail with reference to the accompanying drawings.
Referring to FIG. 1, a typical charge detecting device of a floating diode amplifier type comprises an n-type semiconductor substrate 105, an input gate electrode 101, a floating diode composed of an n.sup.+ -region 102, a source-follower amplifier 108 and a reset transistor 120 composed of n.sup.+ -regions 110 and 111 and a gate electrode 109. The input gate electrode 101 is held at a constant voltage V.sub.OG and serves to input a signal charge fed from a charge transfer section in the solid-state imaging device into the charge detecting means. The floating diode serves to accumulate the signal charge inputted through the input gate electrode 101. The source-follower amplifier 108 serves to detect a variation of a surface potential of the floating diode caused by the signal charge accumulated in the n.sup.+ -region 102 of the floating diode. The reset transistor 120 comprises a source also serving as n.sup.+ -region 102 of the floating diode, a gate electrode 107, a drain 106 and a channel region and serves to drain unnecessary signal charge accumulated in the source after a charge detecting operation.
In the operation of the charge detecting device, when the reset transistor 120 turns on, the unnecessary signal charge is drained from the n.sup.+ -region 102, whereby a surface potential V of the n.sup.+ -region 102 is maintained at a constant reset potential. Subsequently, the reset transistor 120 turns off and a signal charge Q transferred from the solid-state imaging device is inputted into a potential well of the n.sup.+ -region 102 through the input gate electrode 101. This causes a variation in the surface potential of the n.sup.+ -region 102. The variation is outputted as an output voltage V.sub.out through the source-follower amplifier 108. The output voltage V.sub.out is given by EQU V.sub.out =(Q/C.sub.FJ) (g.sub.m R.sub.S)/(1+g.sub.m R.sub.S) (1)
where g.sub.m is the transconductance of the transistor of the source-follower amplifier 108, R.sub.S is the source resistance and C.sub.FJ is the capacitance of the n.sup.+ -region 102. It is therefore understood that the output voltage V.sub.out is proportional to the signal charge Q.
Further, an operation of the reset transistor 120 will hereinafter fully be described in more detail.
Referring to FIG. 5, the reset transistor 120 as a part of the CCD solid-state imaging device normally comprises a buried channel type transistor in which a channel potential .phi..sub.ch varies in proportion to a gate voltage V.sub.G in a wide linear region. The channel potential .phi..sub.ch is therefore given by EQU .phi..sub.ch =k.V.sub.G +.phi..sub.0 ( 2)
where k is the proportional coefficient, .phi..sub.0 is the channel potential when the gate voltage V.sub.G is 0.
The reset transistor 120 turns on and the surface potential of the floating diode is maintained at the constant reset potential by draining completely the unnecessary signal charge accumulated in the floating diode. Required for the realization of this operation is that a high level R.sub.H of reset pulse to be applied to the gate electrode of the reset transistor 120 (as hereinafter referred to as a reset pulse .phi..sub.R) is set so that the channel potential .phi..sub.H is higher than a constant drain voltage V.sub.RD of the reset transistor 120 at the pulse applying time (.phi..sub.H =V.sub.RD +.alpha.) and so that the transfer channel region under the gate electrode of the reset transfer 120 is ordinary satisfied with sufficient electrons during the draining operation. When the channel potential .phi..sub.H is equal to or lower than the drain voltage V.sub.RD of the reset transistor 120, the drain of the signal charge accumulated in the n.sup.+ -region of the floating diode is ultimately regulated by the diffusion of the signal charge. The normal reset operation in which the frequency of the reset pulse to be applied to the gate electrode 107 of the reset transistor 120 is in the range of the frequency from several MHz to tens MHz is impossible for the realization of the complete drain of the unnecessary signal charge. Assuming that the signal charge detecting device is applied to the normal electronic device, the charge detecting device may be applied with a driving voltage common to other ICs. The reset pulse .phi..sub.R of the charge detecting device is therefore set at the amplitude of 5 V and a constant DC voltage, where the high level of the pulse is R.sub.H and the low level of the pulse is R.sub.L.
When the channel potential .phi..sub.H is higher than the constant drain voltage V.sub.RD of the reset transistor 120, the channel potential .phi..sub.L corresponding to the low level R.sub.L of the reset pulse .phi..sub.R is taken into a high potential. In this case, since the potential of the floating diode is set at the constant potential V.sub.RD, maximum quantity of the signal charge of the charge detecting device is proportional to the value (V.sub.RD -.phi..sub.L). When the channel potential .phi..sub.H is set too high, as compared with the constant potential V.sub.RD of the floating diode, the maximum quantity of the signal charge is substantially decreased in proportion to the decrease of the value (V.sub.RD -.phi..sub.L). It is therefore required that the channel potential .phi..sub.H is set at a higher potential than the floating diode potential equal to the drain voltage V.sub.RD and the, maximum quantity of the signal charge of the charge detecting device is equal to or higher than the maximum quantity of the signal charge to be inputted into the floating diode. From the equation (2), the low level of the reset pulse .phi..sub.R to be applied to the gate electrode of the reset transistor 120 is given by EQU R.sub.H =(V.sub.RD +.alpha.-.phi..sub.0)/k, 0&lt;.alpha.&lt;.phi..sub.M( 3)
where .phi..sub.M is the maximum channel potential on the above conditions, V.sub.RD is the drain voltage of the reset transistor 120, .phi..sub.0 is the channel potential when the gate voltage V.sub.G is 0, and k is the proportional coefficient.
Thus, the following problems are associated with the prior art forth above.
An individual charge detecting device requires an external circuit for setting each of a high level R.sub.H and a low level R.sub.L of the reset pulse in response to the channel potential of the reset transistor 120 in order to fulfill a complete reset operation. Further, what is required for only one charge detecting device is also an external circuit for setting each of a high level R.sub.H and a low level R.sub.L of the reset pulse in response to the variable channel potential of the reset transistor 120 in order to fulfill a complete reset operation.